My design flow requires both post synthesis and post implementation timing simulations to be run as part of our verification process.
I have a VHDL only Vivado project and only have a VHDL simulator license for my 3rd party simulator.
How can I run the VHDL timing simulation?
Post Synthesis and Post Implementation Timing Simulations are not supported for VHDL in Vivado.
There is a note in UG900, "Logic Simulation User Guide" outlining this.
"IMPORTANT: Post-Synthesis and Post-Implementation timing simulations are supported for Verilog only. There is no support for VHDL timing simulation."
A suggested workaround for this was to run the "write_vhdl" and "write_sdf" commands from the Tcl Console and run the simulation in your 3rd party simulator standalone.
However this will not work as "write_sdf" will not align to the VHDL netlist because write_vhdl does not support "-timesim" that is needed for timing simulation.