We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57187

System Generator 14.6 - FIR Compiler gives errors in HDLCompiler when used in a subsystem


An attempt to instantiate a FIR Compiler v6.3 block in a configurable subsystem results in the following syntax errors:

External Model firv6_3_CModel:firv6_3_cmodel threw std::exception:
An error occurred during HDL compilation. ERROR:HDLCompiler:1206 - "fir_compiler_v6_3_control.vhd" Line 103: Syntax error near '"'
ERROR:HDLCompiler:1206 - "fir_compiler_v6_3_control.vhd" Line 104: Syntax error near '"' ERROR:HDLCompiler:1206 - "fir_compiler_v6_3_control.vhd" Line 104: Syntax error near '"' ERROR:HDLCompiler:806 - "fir_compiler_v6_3_control.vhd" Line 103: Syntax error near """. ERROR:HDLCompiler:806 - "fir_compiler_v6_3_control.vhd" Line 104: Syntax error near """. ERROR:HDLCompiler:854 - "fir_compiler_v6_3_control.vhd" Line 85: Unit <behavioral> ignored due to previous errors.
Error occurred during "Simulation Initialization".
Reported by:
'wtf/Configurable Subsystem/var_int/INTFIR16'

Is this a known issue?

Can I work around this?


This is a known issue with System Generator 14.6.

To work around this issue, change the name on the block; that is, the new name of the block should not contain a new line character.

In the example below, you can see the block name is "Configurable Subsytem" with a new line; simulating that model produces the errors above. The work-around is applied to the second model below where the block name now contains no new line, "ConfigurableSubsystem".

AR# 57187
Date 08/23/2013
Status Active
Type General Article
  • System Generator for DSP - 14.6
Page Bookmarked