We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57206

2013.2 SysGen - IP Packager Flow Incorrectly Packaging AXI Stream Interface


I am using 2013.2 SysGen and trying to run the IP Packager flow. I have followed all the steps in the guide for ensuring that my ports are packaged as an AXI Stream Interface. However, when I instantiate the newly generated IP in an IPI block diagram, the interface is not correct; several of the signals are not contained within the interface as they should be, but are instead standalone signals.


The following two screenshots show what the incorrect signals (standalone) might look like:



When names are added to signals which drive AXIS gateways, SysGen appends text to the name in the HDL. This is preventing the IP Packager from properly packaging the IP.

To work around this issue, remove the wire names in SysGen.

This issue will be addressed in a future release of the tools.

AR# 57206
Date Created 08/22/2013
Last Updated 12/20/2013
Status Active
Type General Article
  • Vivado Design Suite - 2013.2
  • System Generator for DSP