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AR# 57235

2013.2 Vivado HLS - Step by step instructions to use the Vivado Project generated by VHLS from the C/C++ source code


When using Vivado HLS 2013.2 and later, it is possible to get the tool to generate a Vivado project based on the provided sources and testbench.

This Answer Record provides the steps to follow.

This allows the user to run post-synthesis and post-implementation simulations from Vivado, and to further verify that the RTL behaves as expected after synthesis and implementation.

The RTL testbench created during cosim (from the user's C testbench) is the one used to create the Vivado project.


The step by step flow is:

  1. Run the normal flow - the example below shows the HLS TCL commands, but the procedure is the same from GUI:

    1. csim_design.
    2. csynth_design.
    3. cosim_design -rtl vhdl # or use Verilog : that's the RTL language that will be used for the TB in the Vivado project.
    4. export_design.

  2. A Vivado project (project.xpr) is created in $hls_proj/$solution/impl/vhdl (or the Verilog) directory. Open it with Vivado.

  3. You can Run Behavioral Simulation again, to verify that the RTL exported by the tool behaves correctly.
    Please note that it is logically equivalent to running the previous step 1.3., cosim_design.

  4. Run Synthesis and then run Post-synthesis Functional Simulation.

  5. Run Implementation and then run Post-implementation Functional Simulation.

Note: the VHLS project directory or subfolders may be deleted by the Vivado HLS tool at each new run, so a user backup needs to be done in order keep changes to the generated Vivado project.

There is a limitation to this flow: the AXI interfaces adaptors are not simulated.

Please also remember that the simulation testbench applied on the top level module is converted from C testbench, so for any changes to the source code the user needs to rerun all the steps. 

This is achieved more easily via a TCL script.



Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 57235
Date 05/29/2014
Status Active
Type Solution Center
  • Vivado Design Suite
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.4
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