When using Vivado HLS 2013.2 and later, it is possible to get the tool to generate a Vivado project based on the provided sources and testbench.
This Answer Record provides the steps to follow.
This allows the user to run post-synthesis and post-implementation simulations from Vivado, and to further verify that the RTL behaves as expected after synthesis and implementation.
The RTL testbench created during cosim (from the user's C testbench) is the one used to create the Vivado project.
The step by step flow is:
Note: the VHLS project directory or subfolders may be deleted by the Vivado HLS tool at each new run, so a user backup needs to be done in order keep changes to the generated Vivado project.
There is a limitation to this flow: the AXI interfaces adaptors are not simulated.
Please also remember that the simulation testbench applied on the top level module is converted from C testbench, so for any changes to the source code the user needs to rerun all the steps.
This is achieved more easily via a TCL script.