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AR# 57254

2013.2 Vivado Sysgen - Data mismatch in behavioral simulation for FIR Compiler v7.1

Description

In my Vivado System Generator design, which contains the FIR Compiler v7.1 block, an output data mismatch occurs between the System Generator simulation and the HDL behavioral simulation.

The System Generator results are delayed by few cycles.

Solution

This issue is primarily due to incorrect handling of front padding coefficient data in System Generator while driving the FIR C-Model.

To work around the issue for the FIR Compiler where the reload coefficient feature is enabled and  it is based on co-efficient structure, do the following:

Eliminate the single/multiple delay introduced during System Generator simulation by disabling Hybrid Simulation flow of FIR compiler block.

Hybrid simulation support on FIR Compiler block can be disabled by updating the file located at:

<Install dir>\scripts\sysgen\matlab\xlfircv71_init.m

For example by changing

simulation_type = 'hybrid_sim'

to

simulation_type = 'xsim'

This has been resolved in Vivado System Generator 2013.3.

AR# 57254
Date Created 08/27/2013
Last Updated 04/17/2014
Status Active
Type General Article
Tools
  • System Generator for DSP
  • Vivado Design Suite - 2013.2