UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57274

Vivado 2013.2 - 734 MHz limit for processing system v5.2, need 800 MHz

Description

In Vivado 2013.2 there is a limit of 734 MHz for the CPU clock in the Zynq-7000 Processing System v 5.2. However, for 7Z045 devices, 800 MHz should be available.

How can I address this?

Solution

Vivado 2013.3 tools will allow the user to select  800 MHz.

There is a patch attached to this answer record that allows the selection of 800 MHz for Vivado 2013.2

Copy the patch processing_system_v5_2 into the following location,

"Vivado Installation Directory"\Xilinx\Vivado\2013.2\data\ip\xilinx

You can either overwrite the existing one or rename the existing one as backup.

If the user already has a block diagram design, then remove the processor_system from the block diagram and re-add it again to allow the patch to work


The change can be verified for 800 MHz by the following:

1. Open the generated ps7_init file
2. Search for 0xF8000100 ( PLL_FDIV = 0X30) for multiplier value
    a. Convert to decimal 0X30=48
3. Search for 0XF8000120 (DIVISOR=0X02) for Divisor value
4. Input frequency = 33.333
5. CPU_6X = (Input frequency * PLL_FDIV)/DIVISOR
    a. CPU_6X frequency = (33.333*48)/2 = 800Mhz


As seen here:

   // .. .. .. START: UPDATE FB_DIV
    // .. .. .. PLL_FDIV = 0x30
    // .. .. .. ==> 0XF8000100[18:12] = 0x00000030U
    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00030000U
    // .. .. .. 
    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00030000U),
  // .. .. .. FINISH: REMOVE PLL BY PASS
    // .. .. .. SRCSEL = 0x0
    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
    // .. .. .. DIVISOR = 0x2
    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
    // .. .. .. CPU_6OR4XCLKACT = 0x1
    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
    // .. .. .. CPU_3OR2XCLKACT = 0x1
    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
    // .. .. .. CPU_2XCLKACT = 0x1
    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
    // .. .. .. CPU_1XCLKACT = 0x1
    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
    // .. .. .. CPU_PERI_CLKACT = 0x1
    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
    // .. .. .. 
    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),

Attachments

Associated Attachments

Name File Size File Type
AR57274.zip 1 MB ZIP
AR# 57274
Date Created 08/28/2013
Last Updated 08/29/2013
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • Vivado Design Suite - 2013.2
IP
  • Processing System 7