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AR# 57279

MIG 7 Series DDR3 RDIMM - Clock Driver Enable settings for RC1 may cause initialization failures


Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)

MIG 7 Series DDR3 RDIMM designs set the RC1 Clock Driver Enable control word to enable or disable the four output clocks in the for the SSTE32882 register chip located on the RDIMM. For single rank and dual rank designs, MIG only enables two clocks to conserve power. However, for the Micron MT9JSF25672PZ, the default clock drivers enabled are set incorrectly and may cause initialization failures in hardware.


The SPD module on the RDIMM can be read to determine which specific clock outputs are used and should be enabled, but MIG does not have the capability to read from the SPD so to resolve this issue all 4 clock drivers are enabled. 

To work around the issue, the following RTL changes can be made inside mig_7series_v2_0_ddr_phy_init.v:

localparam REG_RC1 = 8'b00000001;

Revision History:
08/28/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 57279
Date Created 08/28/2013
Last Updated 09/03/2013
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series