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AR# 57325

VC709 FPGA Connectivity Kit 2013.2 TRD - Users may encounter an error when simulating the Design using ModelSim


If you are using the ModelSim Simulation Flow in the VC709 Connectivity Targeted Reference Design (v2013.2), you may experience some errors that prevent the ModelSim simulator from running all the way through simulation.

An example of what can occur in the ModelSim console is below:

# Top level modules
# Model Technology ModelSim SE-64 vlog 10.2c Compiler 2013.07 Jul 18 2013
# ** Error: /export/ssd/proj/Cheetah_FPGA/devel/mliang/Cheetah/z_VC709_XC7VX690T-2FFG1761CES_fpga_PCIe_ptypes/v7_xt_conn_trd/ip_cores/dma/netlist/eval/dma_back_end_axi_enc.v(1): near "XlxVHYEB": syntax error, unexpected IDENTIFIER, expecting class
# ** Error: /export/ssd/Mentor/Modelsim_se_10_2_c/modeltech/linux_x86_64/vlog failed.
# Error in macro /export/ssd/proj/Cheetah_FPGA/devel/mliang/Cheetah/z_VC709_XC7VX690T-2FFG1761CES_fpga_PCIe_ptypes/v7_xt_conn_trd/vivado/project_1/xt_connectivity_trd.sim/sim_1/behav/board.do line 394
# /export/ssd/Mentor/Modelsim_se_10_2_c/modeltech/linux_x86_64/vlog failed.
# while executing
# "vlog +define+USE_PIPE_SIM=1 +define+SIMULATION=1 +define+USE_DDR3_FIFO=1 +define+USE_XPHY=1 +define+NW_PATH_ENABLE=1 +define+x4Gb=1 +define+sg107E=1 ..."


In 2013.2, running the QuestaSim / ModelSim simulation will require a different NWL DMA model than the one included in the Vivado project by default.

To run a QuestaSim / ModelSim simulation:

  1. click Simulation Settings under the Project Manager section of the GUI, and verify that the Target Simulator is set to ModelSim / QuestaSim.
  2. Then click OK.  Next, click Run Simulation -> Run Behavioral Simulation. This will open up ModelSim / QuestaSim and you will eventually see an error:
    "<path>/dma_back_end_axi_enc.v(1): near "XlxVHYEB": syntax error..." as shown in the Description above. This is because the encrypted netlist used for implementation and Vivado synthesis is not recognized by ModelSim/QuestaSim.
  3. To run the simulation to completion, you will need to edit board.do in v7_xt_conn_trd/vivado/project_1/xt_connectivity_trd.sim/sim_1/behav and change line 465 from using v7_xt_conn_trd/ip_cores/dma/netlist/eval/dma_back_end_axi_enc.v
    to using v7_xt_conn_trd/ip_cores/dma/models/mti/dma_back_end_axi.vp
  4. Then, use the up arrow in ModelSim / QuestaSim's transcript window to bring up the previously run command which should be -do <path>/board.do.
  5. Hit enter to execute board.do.
    The simulation should now run all the way to the finish.

This solution is also described in the readme.txt of the VC709 Connectivity TRD design zip file.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51901 Virtex-7 FPGA VC709 Connectivity Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 57325
Date Created 08/30/2013
Last Updated 10/28/2013
Status Active
Type General Article
  • Virtex-7
Boards & Kits
  • Virtex-7 FPGA VC709 Connectivity Kit