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AR# 57342

Virtex-7 FPGA Gen3 Integrated Block for PCI Express core SRIOV Example Design Simulation

Description

This answer record describes required modification to the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core Example Design to simulate SRIOV by reading and writing to the confugration space of PFs and VFs, in a downloadable PDF to enhance its usability.

Answer records are Web-based content that are frequently updated as new information becomes available. Please visit this answer record periodically to obtain the latest version of the PDF.

Solution

Single Root I/O Virtualization (SR-IOV) is a mechanism defined by PCI-SIG that allows a single Physical PCIe device to be multiple PCIe devices. This is realized with Physical Function (PF) and Virtual Function (VF). PF is a full-fledged PCIe entity with its own entire PCIe configuration space whereas VF is a subset of a PF and contains minimal configuration space definition.

The simulation will run into an error message when simulating the out-of-the-box example design with the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core configured for SRIOV. It is because the current example design simulation testbench (v2.1) does not support SRIOV. This document describes in detail the modification required in the example design test bench to be able to read and write configuration space of the configured PFs and VFs.

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Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56802 Xilinx PCI Express Long Form Answer Records N/A N/A
AR# 57342
Date Created 09/03/2013
Last Updated 11/12/2013
Status Active
Type General Article
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)