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AR# 5736

1.5i Virtex Map - Bus error (core dumped) on V300 design


Keywords: map, virtex, core dump, bus error, pack registers in iob

Urgency: Normal

General Description:

m1.5.28 virtex 300 design. synplicity 5.08.

When running map with -pr b option (pack both input/output registers in IOB),
map exits with bus error (core dumped) as follows:

M1_5.28: zeppelin% map -pr b -o tx_fpga_map.ncd tx_fpga.ngd
map: version M1.5.28i
Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved.
Reading NGD file "tx_fpga.ngd"...
Using target part "v300bg432-4".
Processing logical timing constraints...
..Removing unused or disabled logic...
Checking design components...
Pushing bubbles ...
Collapsing logic...
Bus Error (core dumped)



1. run map with -pr o (pack registers in IOB output register)
2. run map without -pr option (no greedy packing of registers into IOBs)

This issue has been fixed in version 2.1i.
AR# 5736
Date Created 02/23/1999
Last Updated 04/25/2000
Status Archive
Type General Article