We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57371

SDK 14.6 - How do you set up a shared memory space between the CPU0 and CPU1 on a Zynq platform?


In a simple application, I have the variables declared in the CPU0's global area in main.c:

int Temp = max_temp;

However, I want to place them in a common CPU0/CPU1 region @ base address 0xFFFF0000.

How can I achieve this?


The simplest way to do this would be to define a special section in the linker.

For example, in your linker add a new section:

.shared_section :{*(.shared_section)} > 0xffff0000

Then, in your application, assign the variables to that section:

int Temp__attribute__((section(".shared_section")));

AR# 57371
Date Created 09/05/2013
Last Updated 09/05/2013
Status Active
Type General Article
  • EDK - 14.6
  • Vivado Design Suite - 2013.2