We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57396

2013.2 - Vivado AXI IIC will not work and MicroBlaze hangs when reading 1 byte when PAGE_BYTE in xiic_eeprom_example.c is set to 1


My design was migrated from XPS to Vivado, but the Vivado Design does not work.
To troubleshoot, I took the Xilinx example "xiic_eeprom_example.c".

This example works with XPS and Vivado.

The example writes and reads 16 bytes.

After changing the PAGE_SIZE value from 16 to 1, the MicroBlaze hangs with the Vivado design. 

In XPS the example also works with PAGE_SIZE value 1.


This issue is due to be fixed in Vivado 2013.3.
AR# 57396
Date Created 09/09/2013
Last Updated 03/30/2015
Status Active
Type General Article
  • SoC
  • FPGA Device Families
  • Vivado Design Suite
  • Vivado Design Suite - 2013.2
  • AXI IIC Bus Interface