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AR# 57409

Virtex-7 SSIT devices ICAP access limitation

Description

When a 7 series SSI FPGA is in master SPI x2 or x4 configuration mode, the Master and Slave SLR ICAPE2 sites are not functional.

The FPGA is in master SPI x2 or SPI x4 mode when the MODE pins are set to SPI mode and BITSTREAM.CONFIG.SPI_BUSWIDTH is set to 2 (dual) or 4 (quad), respectively.

Solution

Affected devices:  7 Series SSI FPGAs
 
  • XC7V2000T
  • XC7VX1140T
  • XC7VH580T
  • XC7VH870T

Design impact:

The ICAPE2 primitive is not functional.
Example applications that use ICAPE2 include:
  • SEM IP
  • Partial reconfiguration
  • Tandem configuration for PCIe
  • Design-initiated multiboot.

Work-arounds:
  • Use SPI in x1 mode.
  • Use configuration solutions other than SPI mode, for example master BPI mode.
AR# 57409
Date Created 09/09/2013
Last Updated 08/06/2014
Status Active
Type General Article
Devices
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.2