My design is failing with the following placement error for a BUFMRCE driving a BUFR.
I have these buffers constrained to the same clock region which should be routable according to the error message.
Why does this error occur?
ERROR: [Place 30-129] Unroutable Placement! A BUFMRCE / BUFR component pair is not placed in a routable site pair. The BUFMRCE component can use the dedicated path between the BUFMRCE and the BUFR if the BUFMRCE is placed in the same clock region, the clock region above or the clock region below as the BUFR. In parts with multiple Super Logic Regions(SLR), the BUFMRCE and the BUFR components are required to be in the same SLR.
U_rtmac_fpga/U_rtmac_20g_data_path_dp1/U_serdes_pktbus_2lane_if_dual/U_serdes_pktbus_2lane_if0/genblk1.U_serdes_pktbus_2lane_gt/U_DATA_IF_BUFMR (BUFMR.O) is locked to BUFMRCE_X1Y4 (in SLR 0)
The loads are distributed to 1 user pblock constraints.
In addition, there are 0 loads not in user pblock constraints.