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AR# 57489

2013.2 SysGen - Upgrading model with DDS v5.0 to DDS v6.0 causes compilation error when simulating

Description

I have migrated my design containing DDS v5.0 from 14.6 SysGen to 2013.2 SysGen. The model upgrade flow in 2013.2 succeeds, but when simulating the following error occurs:

Input port's 's_axis_phase_tdata_phase_in' is expected to be Ufix_10_10, but is UFix_10_0. Error occurred during "Rate and Type Error Checking".

What is the problem?

How do I get around this error?

Solution

The data-type requirements for this point have changed slightly for DDS v6.0 in SysGen.

To work around the issue, use a re-interpret block to force the proper binary point (in this example, the binary point was forced to be 10). This costs nothing in hardware, removes the error, and allows the core to work with the exact same functionality as v5.0.

AR# 57489
Date Created 09/17/2013
Last Updated 01/02/2014
Status Active
Type General Article
Tools
  • System Generator for DSP
  • Vivado Design Suite - 2013.2