We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57500

Vivado 2013.2 - Tandem PCIe is not linking up


Opt during implementation looses the pblock property for some FSM registers that were transformed during opt. This causes stage1 registers to be placed in stage2, thus the stage1 design does not work properly.

Tandem PROM works as expected. Loading stage1, then stage2, and then booting the PC works as expected.


How to tell if this is the issue you are experiencing:

  1. Open the implemented design.
  2. Run the following command to report any cells in the PCI Express Hierarchy, but that are NOT in a PBLOCK:
# Filter on "primitive name is in the IP Core" && "primitive is not assigned to a pblock" && "primitive is not a ground connection"
~ "pcie_x8gen2_axi_st_ip_i/inst/*" && PBLOCK == "" && PRIMITIVE_TYPE != "OTHERS.others.GND"
} ]


Create a tcl.pre file that puts these components back into the main pblock after opt has been run.

# Example Command to add the script as a opt tcl.post file in the implementation settings. Path must match your file.
set_property STEPS.OPT_DESIGN.TCL.POST /tandem/implement/tpcie/addMisplacedCellsToPblock.tcl [get_runs impl_1]
# TCL Script to put misplaced cells back into the main PBLOCK
set misplacedCells [get_cells -hierarchical -filter { NAME=~ "pcie_x8gen2_axi_st_ip_i/inst/*" && PBLOCK == "" && PRIMITIVE_TYPE != "OTHERS.others.GND"} ] set mainPblock [get_pblocks main_pblock_boot] if { $misplacedCells != "" } {add_cells_to_pblock $mainPblock $misplace
ls }

This issue will be fixed in Vivado Design Suite 2013.3.

AR# 57500
Date Created 09/18/2013
Last Updated 09/26/2013
Status Active
Type General Article
  • Kintex-7
  • Artix-7
  • Virtex-7
  • Vivado Design Suite - 2013.2
  • PCI-Express (PCIe)