This answer record contains the Release Notes and Known Issues for the ZYNQ7 Processing System BFM and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2015.1 and before.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
ZYNQ7 Processing System BFM Core IP Page:
*Note: From Vivado 2016.1, Zynq BFM is hidden from Vivado. It is only accessible through the Processing System7 IP.
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
|v2.0 (Rev 5)||2015.3|
|v2.0 (Rev 4)||2015.2|
|v2.0 (Rev 3)||2014.2|
|v2.0 (Rev 2)||2014.1|
|v2.0 (Rev 1)||2013.4|
|v1.0 (Rev 1)||2013.2|
For general guidance on how to use this core, please refer to Zynq-7000 SoC Bus Functional Model Data Sheet for more details.
Here are some example designs and extra information for the core.
|(Xilinx Answer 55345)||Zynq-7000 BFM Example Design|
Known and Resolved Issues
The following table provides known issues for Zynq-7000 SoC Bus Functional Model core.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions. Please also review the Change log for more details.
|Article Number||Article Title||Version Found||Version Resolved|
|(Xilinx Answer 67322)||Zynq-7000 BFM - Fatal: (SIGSEGV) Bad handle or reference during BFM API calls||See Answer Record||See Answer Record|
|(Xilinx Answer 67207)||Vivado 2016.1 AXI BFM, Zynq BFM - AXI BFM and Zynq BFM do not correctly terminate WSTRBs of unaligned burst writes||2016.1||See Answer Record|
|(Xilinx Answer 61011)||Zynq-7000 Bus Functional Model v2.0 - Enabling the static remap parameter causes the simulation to hang||v2.0||See Answer Record|
|(Xilinx Answer 60949)||2014.2 - Zynq BFM example design fails simulation in VCS and IES||2014.2||See Answer Record|
|(Xilinx Answer 62030)||ModelSim simulation of Zynq BFM throws error on non zero reset value||2014.2||See Answer Record|
|(Xilinx Answer 62254)||Zynq BFM simulation - Invalid release of reset||v2.0 (Rev 3)||See Answer Record|
|(Xilinx Answer 62679)||2014.2 Vivado - AXI BFM - Zynq BFM stop responding after a series of random reads||v2.0 (Rev 3)||2015.2|
|(Xilinx Answer 59314)||2013.4 Zynq BFM - Zynq BFM does not respond to READ, RVALID is not inserted||v2.0 (Rev 1)||See Answer Record|
|(Xilinx Answer 58097)||Vivado Simulator 2013.2 - Fatal Error simulating Zynq BFM example design||2013.2||2013.3|