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AR# 57524

MIG 2.3 Virtex-5 - DDR2 - SSTL18_II_DCI on ODT and CKE causes calibration failure.

Description

There is an option called "DCI for Address/Control" in the MIG GUI for DDR2 on Virtex-5.

If this option is enabled, all address/control signals use SSTL18_II_DCI.

During FPGA configuration, DCI might generate pulse on ODT and CKE.

This violates the DDR2 JEDEC standard and will lead to MIG IP calibration failure. 

Solution

The solution is to disable DCI for ODT and CKE.

Using only SSTL18_II can solve this problem. 

Revision History:
01/20/2015 - Initial Release
AR# 57524
Date Created 09/21/2013
Last Updated 03/05/2015
Status Active
Type General Article
Devices
  • Virtex-5
  • Virtex-5QV
  • Virtex-5Q
Tools
  • ISE
IP
  • Memory Interface and Controller