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AR# 57549

Vivado Simulator - "[VRFC 10-1089] near character ‘0’ ; 3 visible types match here" when directly instantiating Verilog modules in VHDL


I am directly instantiating Verilog modules in VHDL similar to the following:

module_i :  entity work.module

Port map


I am receiving the following error message:

ERROR: [VRFC 10-1089] near character 0 ;  3 visible types match here ["module.vhd":<line number>]


This can occur when constants are assigned to any of the ports:

port_a => '0',


port_a => std_logic('0'),

To work around this issue, use a qualified expression to assign the constant port value:

port_a => std_logic'('0'), 

Alternatively, a constant signal can be defined and connected to the port:

constant GND : std_logic := '0';


port_a => GND,

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58881 Xilinx Simulation Solution Center - Design Assistant - Language Support N/A N/A
AR# 57549
Date 09/16/2014
Status Active
Type General Article
  • Vivado Design Suite
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