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AR# 57552

Clocking Wizard v5.1, Vivado 2013.3 - Release Notes and Known Issues

Description

This Release Note is for the Clocking Wizard v5.1, released in Vivado 2013.3 tools, which contains the following:

  • General Information
  • New Features
  • Bug Fixes
  • Known Issues

Solution

General Information

The Clocking Wizard v5.1 supports the 7 series FPGAs and Zynq devices.

New Features in v5.1

  • AXI4-Lite interface to dynamically reconfigure MMCM/PLL
  • Tool tips added to the GUI
  • Jitter and Phase error values to IP properties
  • Support for Cadence IES and Synopsys VCS simulators
  • Enhanced support for IP Integrator

Bug Fixes in v5.1

  • Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
  • Fixed precision issues between displayed and actual frequencies
  • Reduced warnings in synthesis and simulation 
  • Enhanced support for IP Integrator

Known Issues in v5.1
There are currently no known issues.

AR# 57552
Date Created 09/24/2013
Last Updated 09/27/2013
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2013.2