UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57566

Why does the IBIS Simulation look better with an external resistor instead of the optional internal termination resistor?

Description

Why does my IBIS simulation for an input/receiver look better with an external termination resistor instead of with the device's internal termination resistor? (DIFF_TERM, DCI, or IN_TERM)

Solution

When performing IBIS simulations of any receiver/input for the purpose of analyzing what the receiver/input buffer is seeing for the signal, it is important to select in your simulator the option to view the signal "Always at the Die", rather than "Always at the Pin".

This places the simulation probe "inside" of the package parasitic resistance, capacitance, and inductance values, essentially at the device's die-pad, which will also be closer to the device's termination circuits (DIFF_TERM, DCI, or IN_TERM). If you observe the signal at the device's pin instead, the signal will often look distorted due to the signal integrity effects of passing through the package parasitic network, reflecting off the pad (where it is terminated), and traveling back through the package parasitic network to the pin. On the other hand, simulations where an external termination resistor is used, if you place the probe at the Pin, it will be on the same side of the package parasitic RLC as the termination structure, and will generally have a better looking signal quality.




Running the simulation with the probe selected to be "Always at the pin" is useful whenever you are trying to correlate your simulation results to an actual hardware oscilloscope measurement. Then you will want to place the simulation probe as close as possible to the actual probe point on the board.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
31922 Virtex/Spartan - There is noise/glitch on an input; however, the FPGA design works correctly N/A N/A
AR# 57566
Date Created 06/05/2014
Last Updated 06/06/2014
Status Active
Type General Article
Devices
  • SoC
  • FPGA Device Families
  • Artix-7
  • More
  • Extended Spartan-3A
  • Kintex-7
  • Spartan-3
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6
  • Virtex UltraScale
  • Virtex-4
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • Virtex-5
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Virtex-7 HT
  • Zynq-7000
  • Less