In 2013.1, the generated code contains a RESET port for my Built-In FIFO blocks.
However I cannot see this port in the System Generator model.
The port is not exposed on the FIFO block.
Why does this occur and how can I work around this issue?
Since 2013.1, the Built-In FIFO always exposes the RESET port.
This is correctly being added in the generated HDL for the block, but the FIFO block in the model is not being updated.
It will only update to expose the RESET port if the FIFO block's configuration GUI is opened and re-saved.
At this point, the RESET port will be exposed in the model and connected as needed.
As a result, the work-around is to open the FIFO block from the System Generator model and save it again.
In 2013.3, the RESET port in the Built-In FIFO is again configurable.
It is possible to select it through the FIFO block customization GUI.