UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 57604: Vivado System Generator 2013.3 - Why is the fractional width on the "reload_tdata_data" port no longer dynamic in the FIR Compiler?

AR# 57604

Vivado System Generator 2013.3 - Why is the fractional width on the "reload_tdata_data" port no longer dynamic in the FIR Compiler?

Description

Why is the fractional width on the "reload_tdata_data" port no longer dynamic in the FIR Compiler?

Previously this could be configured as Fix_X_Y in the GUI.

Solution

Previously, the fractional width of the "reload_tdata_data" port of FIR Compiler IP was dynamic and it depended on the user configuration (GUI settings) which created some inconsistency. 

Therefore, to make it more consistent and general, the fractional bit is always maintained as '0' starting from the 2013.3 release.

The old designs can be used by introducing a Re-Interpret block between the source block and the "reload_tdata_data" port of the FIR Compiler.

This will not break any functionality.

AR# 57604
Date 05/01/2014
Status Active
Type General Article
Tools
  • System Generator for DSP
  • Vivado Design Suite - 2013.3
IP
  • FIR Compiler