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AR# 57610

14.x System Generator - The AXI FIFO block will use block RAM when configured to use DRAM


I have configured my AXI FIFO block to use "Common Clock Distributed RAM" for the implementation type but when the design is implemented it appears to use a block RAM instance.

Why does this occur?


This is a known issue where the XCO file being created by System Generator for the IP core is incorrect and does not contain the correct parameter setting, and as a result it defaults to "Common Clock Block RAM".

This will lead to unexpected resource utilization. This issue does not occur when using Vivado System Generator and only occurs with ISE System Generator.

AR# 57610
Date Created 09/26/2013
Last Updated 09/26/2013
Status Active
Type General Article
  • System Generator for DSP - 14.1
  • System Generator for DSP - 14.2
  • System Generator for DSP - 14.3
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  • System Generator for DSP - 14.4
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