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AR# 57624

14.7 - EDK BSB - ZC702 board has incorrect GPIO_SW bitwidth

Description

The Base System Builder (BSB) generated design for a ZC702 board has incorrect GPIO_SW bit width.

The BSB generates one bit GPIO_SW axi_gpio, whereas the board has a two bit GPIO_SW.

 How can this issue be fixed?

 

Solution

To work around this issue, the generated .mhs file and .ucf files need to be corrected.
 
The bit width of the GPIO_SW_TRI_O port must be increased to 2 bit and the constraints updated.

The changes should be made as below:
 
Files
BSB Generated code
Corrected
MHS (change the gpio parameter to 2 of instance GPIO_SW)
PARAMETER C_GPIO_WIDTH = 1
PARAMETER C_GPIO_WIDTH = 2
MHS (change the external port width to 2bit)
PORT GPIO_SW_TRI_IO = GPIO_SW_TRI_IO, DIR = IO
PORT GPIO_SW_TRI_IO = GPIO_SW_TRI_IO, DIR = IO, VEC = [1:0]
UCF (change existing constraint to vector type)
NET GPIO_SW_TRI_IO LOC = "G19"  |  IOSTANDARD = "LVCMOS25";
NET GPIO_SW_TRI_IO[0] LOC = "G19"  |  IOSTANDARD = "LVCMOS25";
UCF  (Add constraint for 2nd bit pin)
-
NET GPIO_SW_TRI_IO[1] LOC = "F19"  |  IOSTANDARD = "LVCMOS25";
 
AR# 57624
Date Created 09/26/2013
Last Updated 01/27/2015
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • EDK - 14.6
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit