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AR# 57662

MIG 7 Series AXI, ECC Enabled, 4:1 - dbg_rddata_r is half the width of dbg_rddata

Description

Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)

For MIG 7 Series AXI, ECC Enabled, and 4:1 clock ratio designs, "dbg_rddata_r" is only half the width of "dbg_rddata". Therefore, when an ECC error occurs, half of the registered data is lost.

Solution

To fix the issue, apply the following RTL changes to mig_7series_2_0_memc_ui_top_axi.v.

Change:

Line 960: reg [4*DQ_WIDTH-1:0]         dbg_rddata_r;

To:

Line 960:     reg [2*nCK_PER_CLK*DQ_WIDTH-1:0]         dbg_rddata_r;

Revision History
09/26/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 57662
Date Created 09/26/2013
Last Updated 09/26/2013
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series