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AR# 57673

2013.2 Vivado HLS - Errors are returned "E [RTGEN-102] Read value from an output port / E [HLS-103] RTL output"


Vivado HLS stops with the following error, at the RTL generation phase:

@I [RTGEN-500] Setting interface mode on function 'top' to 'ap_ctrl_hs'.
@E [RTGEN-102] Read value from an output port: 'top/a_address' to 'top/a_address_read_wireread_fu_54_p2'.
@E [HLS-103] Read value from an RTL output.
Synthesis failed.

The code is similar to the following:

void top (   int*  a,   unsigned int a_address ) {
#pragma HLS INTERFACE ap_bus depth=1024 port=a
//some code etc..


There is a name clash in the generated RTL, hence the error.

The RTL port names are derived from the C name, and the port "a" with interface ap_bus will generate a RTL port named a_address which clashes with the other C top-level port having the same name.

To work around this issue, change the C port variable "a_address" to something else, (e.g., a_offset, or my_a_address, etc.).

This issue is currently under review.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47429 Xilinx Vivado HLS Solution Center - Top Issues N/A N/A
AR# 57673
Date Created 09/27/2013
Last Updated 09/30/2013
Status Active
Type Known Issues
  • Vivado Design Suite - 2013.2