This answer record contains debugging tips concerning reference clock, termination, or signal integrity problems.
Note: This answer record is part of the Xilinx HSSIO Solution Center (Xilinx Answer 37181).
The Xilinx HSSIO Solution Center is available to address all questions related to HSSIO.
Whether you are starting a new design or troubleshooting a problem, use the HSSIO Solution Center to guide you to the right information.
The reference clock is the heart of the HSSIO system and it must be extremely clean. The following answer records describe the phase noise limits for HSSIO reference clock inputs.
In order to avoid reducing the system's jitter budget, these guidelines should be followed.
|(Xilinx Answer 44549)||7 Series GTX/GTH/GTP Reference Clock Phase Noise Masks|
|(Xilinx Answer 43154)||Spartan-6 GTP Reference Clock Phase Noise Mask|
|(Xilinx Answer 42987)||Virtex-6 GTH Reference Clock Phase Noise Mask|
|(Xilinx Answer 38506)||Virtex-6 GTX Reference Clock Phase Noise Mask|
|(Xilinx Answer 35940)||How to Convert Oscillator Phase Noise to Timer Jitter|
For UltraScale, the Reference Clock Phase Noise Mask has been added to the Data Sheets - see (DS892) and (DS893).
Any phase noise above these levels will directly reduce the system's margin and make the data eye smaller.
Fabric-based reference clock:
Fabric-based reference clocks (typically called GREFCLK or GTGREFCLK or PERFCLK) are no longer allowed to be used for HSSIO as their jitter performance can be degraded leading to sub-optimal transceiver performance.
See (Xilinx Answer 53500) for details.
The criteria that must be met when selecting an oscillator as a reference clock for HSSIO are listed in the Transceiver User Guides -> Board Design Guidelines -> Reference Clock section.
For 7 series and UltraScale FPGAs, the "RX Analog Front End" section of the user guide shows how to make the proper termination selections in the wizard.
In the 7 Series Wizard, the default termination setting is not tailored to a particular setup. It is important to set these values appropriately for the intended design.
In the future, the wizard will ask users to input channel loss information, and then make the proper termination selection.
See also (Xilinx Answer 55366).
Make sure to follow the guidelines for the board layout for the RCAL resistor in the Termination Resistor Calibration Circuit.
One mistake that occasionally occurs (on Virtex-5 FPGA) is using the internal AC capacitor along with external AC capacitors.
This usually reduces the channels margin and Bit Error Rate.
If debugging signal integrity issues, it is a good idea to analyze the intended channel layout using IBIS-AMI models.
The channel should be represented with all of its connectors, cables, and PCB lines, using wide band models (0 to 30 GHz at least).
Bias should always be modeled in backplane applications, when the PCB thickness is greater than 2.5 mm, or when the Nyquist frequency is higher than 5GHz.
Some EDA tools can provide a quick indication of the necessary equalizer setup to be used in hardware.