We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57742

Xilinx HSSIO Solution Center - Design Assistant Debugging Clock and Data Recovery Problems


This answer record discusses how to debug Clock and Data Recovery Problems.

Note: This article is part of the Xilinx HSSIO Solution Center (Xilinx Answer 37181)

The Xilinx HSSIO Solution Center is available to address all questions related to HSSIO.

Whether you are starting a new design or troubleshooting a problem, use the HSSIO Solution Center to guide you to the right information.


CDR (Clock and Data Recovery)



The CDR can be tested in the following ways:

  • Transmit known characters and monitor the received data.
  • If 8B10B decoder is enabled, RXDISPERR and RXNOTINTABLE errors will be asserted.
  • For Virtex-5, Virtex-6 GTX, CDR status can be monitored through Loss Of Sync state machine.

Possible causes of CDR problems:

  • REFCLK is not of good quality.
  • CDR is not properly configured. For 7 series, make sure that the RXCDR_CFG is configured for the protocol and ppm variation used. Check for design advisories for the level of silicon used.
    For example (Xilinx Answer 51884) - Design Advisory for Kintex-7 and Virtex-7 FPGA GTX Production Silicon CDR Attribute Updates.
  • Incoming data does not have an adequate eye opening.
  • CDR is not locked.
  • CDR problems can occur if an RX cable is unplugged and replugged; a reset is required for this issue.
  • During long period of idle with the same pattern sent repetitively, the CDR can sometimes have difficulty.
    Setting RXCDRHOLD during this period will avoid this issue.

Important specifications to consider:

  • Runlength (CID) - If the incoming data has no transitions within the Max number of UI specified in this spec, CDR can lose lock.
    A DC balanced signal is required for proper function.

Basic debug steps:

  • Confirm that the REFCLK meets the phase noise mask requirements of the device.
  • Check if the CDR is properly configured.
  • If possible, probe the incoming data eye diagram.
    For 7 series, IBERT can help with monitoring the eye diagram of the RX data.
  • The Eye Scan with MicroBlaze Processor MCS Application Note (XAPP743) shows how eyescan can be integrated into an existing design and run without interrupting normal operation.

Ports to monitor:

  • RXLOSSOFSYNC (not present with 7-series)

Note: The port RXCDRLOCK is only a coarse indicator of CDR lock so should not be used solely as a CDR lock indicator but the incoming data should be monitored.

Xilinx Answer Records:

(Xilinx Answer 43883) - How does RXCDRLOCK work?

Application Notes:

Dynamically Programmable DRU for High-Speed Serial I/O (XAPP875) - Non Integer Data Recovery Unit:

The NI-DRU extends the lower data rate limit to 0 Mb/s and the upper limit to 1,250 Mb/s, making embedded high-speed transceivers the ideal solution for true multi-rate serial interfaces.

AR# 57742
Date Created 09/30/2013
Last Updated 03/16/2015
Status Active
Type Solution Center
  • Artix-7
  • Kintex-7
  • Virtex-7