We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57789

Vivado 2013.2/ISE 14.6, Block Memory Generator v7.3 - Initialization value is incorrect for Simple Dual Port configuration that uses cascade mode for depth > 32K in Memory Generator v7.3 and earlier versions


The values loaded into the Block Memory Generator v7.3 by using a .coe-file are not read out correctly.

If a .coe is loaded into the Memory Generator with a bus width of 16-bit, the coe is read out correctly. If a write is performed to the generator of greater than 16-bits and this value is read out, it is read out incorrectly.


This is known issue with Block Memory Generator v7.3 and earlier versions when core initialization with COE file. This problem occurs for configurations where the Depth is >32k and write widths like 17, 25 etc., which results in using cascading feature of the block RAM in the generated configuration (i.e., few extra bits when divided by 8 or 9).

This issue is reproducible in both ISE 14.6 and Vivado 2013.2 design tools.

The work around is to change the algorithm to "Fixed Primitive" and a primitive type other than "16kx1".

AR# 57789
Date Created 10/03/2013
Last Updated 10/10/2013
Status Active
Type General Article
  • Block Memory Generator