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AR# 57896

MIG 7 Series DDR3/2 - Unused pin in adjacent byte lane requirement for VRN/VRP


UG586 states the following rules within the DDR3/2 Bank and Pin Selection Guides section.

The non-byte group pins, VRN/VRP, can be used for address/control bits if these three conditions are met:

  • For HP banks, DCI cascade is used or the bank does not need the VRN/VRP pins, as in cases where there are only outputs.
  • The adjacent byte group (T0/T3) is used as an address/control byte group.
  • An unused pin exists in the adjacent byte group (T0/T3) or the CK output is contained in the adjacent byte group.

What is the reason for the third restriction?


The pin placed on VRN/VRP has to have a route through the OUT_FIFO.

The CK pins do not use the OUT_FIFO (the clocks are created by the PHASER_OUT) which makes an available route for the pin allocated on VRN/VRP to use.

If the byte lane has unused pins, then there is also a free OUT_FIFO route to use.
AR# 57896
Date 11/04/2014
Status Active
Type General Article
  • Virtex-7
  • Kintex-7
  • Artix-7
  • MIG 7 Series
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