UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57896

MIG 7 Series DDR3/2 - Unused pin in adjacent byte lane requirement for VRN/VRP

Description

UG586 states the following rules within the DDR3/2 Bank and Pin Selection Guides section.

The non-byte group pins, VRN/VRP, can be used for address/control bits if these three conditions are met:

  • For HP banks, DCI cascade is used or the bank does not need the VRN/VRP pins, as in cases where there are only outputs.
  • The adjacent byte group (T0/T3) is used as an address/control byte group.
  • An unused pin exists in the adjacent byte group (T0/T3) or the CK output is contained in the adjacent byte group.

What is the reason for the third restriction?

Solution

The pin placed on VRN/VRP has to have a route through the OUT_FIFO.

The CK pins do not use the OUT_FIFO (the clocks are created by the PHASER_OUT) which makes an available route for the pin allocated on VRN/VRP to use.

If the byte lane has unused pins, then there is also a free OUT_FIFO route to use.
AR# 57896
Date Created 10/09/2013
Last Updated 11/04/2014
Status Active
Type General Article
Devices
  • Virtex-7
  • Kintex-7
  • Artix-7
IP
  • MIG 7 Series