We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57903

LogiCORE IP Serial RapidIO Gen2 v3.0 - Incorrect ooc.xdc file generated with the core


Version Found: v3.0
Version Resolved and other Known Issues: See (Xilinx Answer 54648)

The generated ooc.xdc is not correct when generating the LogiCORE IP Serial RapidIO Gen2 v3.0 core with the "Shared Logic is in Example Design" setting. The port names in the xdc file are different from the actual port names.


This is a known issue only when the 'Shared Logic is in Example Design' setting is selected and the 'Generate Synthesized Design Check Point (.dcp)' option is disabled when generating the core.

This issue will be fixed in a future release of the core.

To work around the issue, modify the port names according to the table below.

Original Name Change to
log_lcl_log_clk log_clk_in
phy_lcl_phy_clk phy_clk_in
gt_clk gt_clk_in
gt_pcs_clk gt_pcs_clk_in
refclk refclk_in
If there is following port in XDC
drpclk drpclk_in
When device status is production and either of Kintex-7 or Virtex-7 or Zynq device is targeted
gt0_qpll_clk gt0_qpll_clk_in
gt0_qpll_out_refclk gt0_qpll_out_refclk_in
When target device is Artix-7
gt0_pll0_clk gt0_pll0_clk_in
gt0_pll0_ref_clk gt0_pll0_ref_clk_in
gt0_pll1_clk gt0_pll1_clk_in
gt0_pll1_ref_clk gt0_pll1_ref_clk_in

Revision History
11/8/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54648 LogiCORE IP Serial RapidIO Gen2 Core - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 57903
Date Created 10/09/2013
Last Updated 11/08/2013
Status Active
Type Known Issues
  • Serial RapidIO