I have three separate EDF netlists, which all contain a module with a common name but with different module definitions (i.e. the port number is not the same).
Now I want to simulate the three designs together by using three exported simulation netlists with the "write_verilog" command.
In ModelSim, simulation fails with the below error.
How can I avoid this conflict?
The "rename_ref" command allows you to change the non-primitive reference names in the current design so that they do not collide with the reference names in another design.
This lets two modules or designs be synthesized or simulated together, while avoiding any name collisions between the two designs.
Open the synthesized design and run "rename_ref" prior to "write_verilog".
This allows MOD1_ to be added to all non-primitive reference cell names in the design.
If the previous module in conflict was named ful_regd_slice, the name is now changed to MOD1_ful_regd_slice in the output simulation netlist.
Because the module name is now different between multiple designs, there will not be any conflict.
For more usage information on "rename_ref", refer to its help.