We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57929

LogiCORE IP G.709 FEC Encoder/Decoder v2.0 (Rev. 2) - Why does the core output incorrect data with 2013.3 Vivado Simulator?


Why does the G.709 FEC v2.0 core output incorrect data when simulating with 2013.3 Vivado Simulator?


This is a known issue when simulating the G.709 FEC v2.0 core with 2013.3 Vivado Simulator.

You can work around this by using another simulation tool, for example Questa or Cadence IES.

Linked Answer Records

Master Answer Records

AR# 57929
Date 08/20/2014
Status Active
Type General Article
  • Vivado Design Suite - 2013.3
Page Bookmarked