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AR# 57945

UltraScale FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the UltraScale FPGA Gen3 Integrated Block for the PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

General Information

Supported devices can be found in the following three locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
  • UltraScale FPGA Gen3 Integrated Block for PCI Express Product Guide (PG156)
 

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v4.4 (Rev2) 2018.1
v4.4(Rev1) 2017.4
v4.4 2017.3
v4.3 (Rev1) 2017.2
v4.3 2017.1
v4.2 (Rev3) 2016.4
v4.2 (Rev2) 2016.3
v4.2 (Rev1) 2016.2
v4.2 2016.1
v4.1(Rev1) 2015.4
v4.1 2015.3
v4.0(Rev1) 2015.2
v4.0 2015.1
v3.1(Rev2) 2014.4.1
v3.1 (Rev1) 2014.4
v3.1 2014.3
v3.0 (Rev1) 2014.2
v3.0 2014.1
v2.0 2013.4
v1.0 2013.3

 

Design Advisory

(Xilinx Answer 64404) Design Advisory for UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2015.1, 2014.4.1) - Link Training failure due to PHYSTATUS not responding to PHY Operations after Device Configuration .

 

Tactical Patch

The following table provides a list of tactical patches for the UltraScale FPGA Gen3 Integrated Block for PCI Express core applicable on corresponding Vivado tool versions.

 

Download from Core Version (after installing the patch) Vivado Version Issues Fixed
(Xilinx Answer 64404) v4.0 (Rev1) 2015.1 (Xilinx Answer 64404), Update #1 in (Xilinx Answer 64838)
(Xilinx Answer 64875)
v4.0 (Rev2)
2015.2 (Xilinx Answer 64875)
(Xilinx Answer 65744) v4.1 (Rev. 65744) 2015.3 (Xilinx Answer 65744)
(Xilinx Answer 65831) v4.1 (Rev. 65831)
2015.3 (Xilinx Answer 65744), (Xilinx Answer 65831)
(Xilinx Answer 66347) v4.1 (Rev. 66347)
2015.4 (Xilinx Answer 66347)
(Xilinx Answer 67111) v4.2 (Rev. 67111) 2016.1 (Xilinx Answer 67111)
(Xilinx Answer 67422) v4.2(Rev. 67422) 2016.2 (Xilinx Answer 67422)
(Xilinx Answer 69308) v4.3 (Rev 69308) 2017.1 (Xilinx Answer 69308)
(Xilinx Answer 69477) v4.3 (Rev 69477) 2017.1 / 2017.2 (Xilinx Answer 69477)
(Xilinx Answer 70061) v4.4 (Rev 2017.3 (Xilinx Answer 70061)



Known and Resolved Issues

The following table provides known issues for the UltraScale FPGA Gen3 Integrated Block for PCI Express core, starting with v1.0, initially released in Vivado 2013.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 70061) PIPE Simulation fails when PIPELINE STAGE of 2 is enabled v4.4 v4.4(Rev1)
(Xilinx Answer 69477) Timed (unsafe) between source clock sys_clk and destination clock pipe_clk v4.3 / v4.3 (Rev1) v4.4
(Xilinx Answer 69308) GT DRP Arbiter Block v4.3 2017.2
(Xilinx Answer 68081) ERROR: [DRC 23-20] Rule violation (HDTC-6) Non-stage-one logic illegally placed - Non-stage-one logic v4.2(Rev1) v4.3
(Xilinx Answer 67422) Link up failure in Gen3 rate after multiple resets v4.2(Rev1) v4.2(Rev2)
(Xilinx Answer 67111) Issue with MSI-X Table Offset Values v4.2 v4.2(Rev1)
(Xilinx Answer 66347)
ASPM Support Update
v4.1 (Rev1) v4.2
(Xilinx Answer 65946) Critical warnings CDC-1 and CDC-7 on the input port clock to user_clk v4.1 v4.2
(Xilinx Answer 65831) GT DRP Ports disabled when Falling Edge Receiver Detect is selected v4.1 v4.1(Rev1)
(Xilinx Answer 65744) Enabling both MSI and MSI-X in the same design v4.1 v4.2
(Xilinx Answer 65776) ERROR: [DRC 23-20] Rule violation (REQP-1881) Tandem_design_fails_with_flash_programming v4.1 v4.1(Rev1)
(Xilinx Answer 65587) CRITICAL WARNING: [Timing 38-282] Negative SETUP slack violation v4.1 v4.1(Rev1)
(Xilinx Answer 64875) PCIe link up failure due to deassertion of CPLLLOCK during reset v4.0 (Rev1) v4.1
(Xilinx Answer 64718) Incorrect refclk_buf location for XCVU095 - FFVC2104, XCVU190 - FLGA2577 and XCVU125 - FLVC2104 v4.0 v4.0(Rev1)
(Xilinx Answer 62668) Example design simulation and synthesis might fail for the VHDL version of the core v3.1 v3.1 (Rev1)
(Xilinx Answer 62471) Timing violations when implementing 2014.2 upgraded design in 2014.3 v3.1 NA
(Xilinx Answer 60072) Timing Violations with non X0Y0 PCIe locations v3.0 v3.0(Rev1)
(Xilinx Answer 60299)
The host system fails to detect PF1 v3.0 v3.0 (Rev1)
(Xilinx Answer 59946) PERSTn signal usage for Virtex UltraScale devices v3.0 v3.0(Rev1)
(Xilinx Answer 59900)
Post Synthesis/Implementation Netlist Functional/Timing Simulation Support v3.0
v4.0

 

Other Information

 

(Xilinx Answer 59901) Enabling GT Wizard mode in Vivado
(Xilinx Answer 61492) I/O Standard selection for PERSTn pins
(Xilinx Answer 64761) Bitstream Loading across the PCI Express Link in UltraScale Devices for Tandem PCIe and Partial Reconfiguration
(Xilinx Answer 65940) [DRC 23-20] Rule violation (HDTC-12) CONFIG cells must be in stage one
(Xilinx Answer 68134) UltraScale and UltraScale+ FPGA Gen3 Integrated Block for PCI Express - Integrated Debugging Features and Usage Guide
(Xilinx Answer 69453)
Hot Plug Support
(Xilinx Answer 66497) Simulation in ModelSim / QuestaSim responds to all Cfg requests with UR

 

Revision History

10/23/2013 Initial Release
12/18/2013 Updated for 2013.4
04/16/2014 Updated for 2014.1
07/15/2014 Added (Xilinx Answer 61492)
10/08/2014 Updated for 2014.3
11/24/2014 Updated for 2014.4
04/15/2015 Updated for 2015.1
06/24/2015 Updated for 2015.2
07/04/2015 Added Design Advisory Answer Record and Tactical Patch section
07/23/2015 Added (Xilinx Answer 64875)
10/06/2015 Updated for 2015.3
11/11/2015 Added (Xilinx Answer 65940)
24/11/2015 Updated for 2015.4
15/1/2016 Added (Xilinx Answer 66347)
04/13/2016 Updated for 2016.1
06/06/2016 Added (Xilinx Answer 67111)
08/06/2016 Updated for 2016.2
07/21/2016 Added (Xilinx Answer 67422)
10/05/2016 Updated for 2016.3
10/15/2016 Added (Xilinx Answer 68081)
01/24/2017 Updated for 2016.4
04/05/2017 Updated for 2017.1
07/05/2017 Updated for 2017.2
07/18/2017
Added (Xilinx Answer 69477)
10/31/2017 Added (Xilinx Answer 70061)
04/18/2018 Added (Xilinx Answer 66497)

Linked Answer Records

Child Answer Records

AR# 57945
Date 04/27/2018
Status Active
Type Release Notes
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)
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