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AR# 57959

Vivado Synthesis - Fails to infer block RAM when the RAM output is driving part of a register bus

Description

In 2014.2 and older versions, if the RAM output is driving part of a register bus, Vivado Synthesis fails to infer block RAM even though ram_style is set to "block".

See the example code below. 

The column_data register bus has one part driven by the RAM output and another part driven by data_in.

(* RAM_STYLE="BLOCK" *)
reg [7:0] lineMem [0:31];
   
reg [15:0]     column_data = 0;
reg   [ADDR_BITS - 1:0]   line_mem_read_address  = 0;

always @(posedge clk) begin
       column_data[7:0]     <= lineMem[line_mem_read_address];
       column_data[15:8]   <= data_in;
end

Solution

This issue is fixed in the 2014.3 release.

There are two work-arounds that can be used for prior releases:

  • Put the splitting register bus assignments into separate always blocks or processes:

always @(posedge clk)
       column_data[7:0]     <= lineMem[line_mem_read_address];
always @(posedge clk)
       column_data[15:8]   <= data_in;

  • Use temporary intermediate signals so that the RAM output signal is not assigned to part of a register bus:

reg  [7:0]           data_in_r;
reg  [7:0]           output_data_from_ram;
always @(posedge clk) begin
       output_data_from_ram     <= lineMem[line_mem_read_address];
       data_in_r   <= data_in;
end
always @* begin
     column_data[15:8] =  data_in_r;
     column_data[7:0]   =  output_data_from_ram; 
    end

AR# 57959
Date Created 10/15/2013
Last Updated 10/08/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite