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AR# 57962

Sysgen 14.x - Connections in the HDL netlist created do not mirror the connections made in the Sysgen MDL leading to incorrect functionality


The HDL Netlist code created from System Generator does not show the correct connections through the design when the "Bus Creator" block is used in a design and subsystem entities are reused in the HDL generated by Sysgen for that design.

Are there any work-arounds available to avoid this issue with ISE Sysgen?


This is a known issue affecting ISE System Generator. The issue does not occur in Vivado System Generator.

Work-arounds exist for ISE System Generator as follows:

  • Prior to the 14.7 Sysgen release, it is necessary to add a dummy block to the subsystem in your Sysgen design to ensure subsystem reuse does not occur (e.g., add an ASSERT block to a signal will not change functionality, but force Sysgen not to reuse the entity when generating the netlist).
  • Post 14.7, it will be possible to turn off the entity reuse feature in Sysgen as follows:
    • Use following commands at MATLAB console:
      % p = xlGetPrefs                      ->  (this shows a list of already set Sysgen Prefs)

      % p.no_entity_reuse=1
      % xlSetPrefs(p) % n = xlGetPrefs                      ->  (check to make sure new Sysgen Pref is set correctly)
  • Open design model
  • Run netlist generation
AR# 57962
Date Created 10/15/2013
Last Updated 01/30/2014
Status Active
Type General Article
  • System Generator for DSP - 14.1
  • System Generator for DSP - 14.2
  • System Generator for DSP - 14.3
  • More
  • System Generator for DSP - 14.4
  • System Generator for DSP - 14.5
  • System Generator for DSP - 14.6
  • System Generator for DSP - 14.7
  • Less