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AR# 57966: Design Advisory for 7 Series - ISERDES behavior after a reset
Design Advisory for 7 Series - ISERDES behavior after a reset
The 7 series ISERDES can have a different bit alignment after a reset in certain configurations.
The reset should always be de-asserted synchronously to the CLKDIV domain.
This behavior is characterized by:
A 2-bit slip in the parallel output data in DDR mode.
A 1-bit slip in the parallel output data in SDR mode.
It is independent of the ISERDES width being used, and can only occur in NETWORKING mode.
The slip in data only occurs after reset, and does not re-occur in following operations regardless of whether the bit slip operation of the input serdes is used or not.
An ISERDES reset uses both the CLK and CLKDIV clock domains.
Correct operation occurs when the CLK domain is phase advanced with respect to the CLKDIV domain.
When this phase separation is not adequate, then the parallel data output alignment can be different from the default alignment.
When only one ISERDES is used, this behavior is irrelevant.
When multiple ISERDES are used in a bus structure, and the user is performing bit alignment based on a known training pattern, then this behavior is irrelevant.
When multiple ISERDES are used in a bus structure and there is no possibility of bit alignment based on a training pattern, then this behavior can cause incorrect data reception.
The suggested work-around depends on the clock topology used.
CLK/CLKDIV are being driven by a BUFIO/BUFR combination. The BUFIO/BUFR are being driven from a common source, either an input signal or an MMCM.
In this case, a fix has been made to Vivado 2014.3 to add 100 ps of delay to the BUFR to guarantee correct operation of the ISERDES.
All BUFR's are affected by the above fix.
There is a hidden bitstream property added to Vivado 2014.3 to control the above behavior, BITSTREAM.GENERAL.BUFR_DELAY. This takes values of ENABLE and DISABLE, ENABLE is the default.
CLK/CLKDIV are being driven from two BUFG or BUFH clock buffers, which are typically sourced from an MMCM or PLL.
In this case, it is suggested that the designer add a *negative* phase shift to the MMCM or PLL output that eventually drives the ISERDES CLK signal. The phase shift should be a minimum of 150ps and a maximum of the bit period of CLK for the ISERDES *minus* 150ps. For example, if CLK to the ISERDES is 500 MHz, then the valid range of phase shift would be 150ps to 1.85ns.