We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 57980

Vivado 2013.2 - Vivado Synthesis generates incorrect logic and connects output port to ground


If I run Vivado Synthesis on my design, it generates incorrect logic and connects output port to ground with the following warning message:

[Synth 8-3917] design bja_stat has port stat_event_gnt driven by constant 0 

The same design works with the Vivado 2013.1 tool.


This condition occurs only when you have a set of four or more compares against a constant and the output of that compare drives a port of the module.

To get around this issue, the following TCL parameter can be used,

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter optimizeConstantEq false"

This issue has been fixed in 2013.3.

AR# 57980
Date 04/16/2014
Status Active
Type Known Issues
  • Artix-7
  • Artix-7Q
  • Kintex-7
  • More
  • Kintex-7Q
  • Virtex-7
  • Virtex-7Q
  • Less
  • Vivado Design Suite - 2013.2
Page Bookmarked