If I run Vivado Synthesis on my design, it generates incorrect logic and connects output port to ground with the following warning message:
[Synth 8-3917] design bja_stat has port stat_event_gnt driven by constant 0
The same design works with the Vivado 2013.1 tool.
This condition occurs only when you have a set of four or more compares against a constant and the output of that compare drives a port of the module.
To get around this issue, the following TCL parameter can be used,
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter optimizeConstantEq false"
This issue has been fixed in 2013.3.