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AR# 57981

Vivado Synthesis - Do you pack ROM into block RAM when there is an incompatible interface on the input side?


If a ROM in the HDL code has a sequence such as input register + ROM + output register, and the input register is incompatible such as Asynchronous, Vivado Synthesis does not allow ROM to be packed into the block RAM.

How do I fix this issue? Is there a work-around?


The work-around is to apply "Keep" in the interface between input register and the ROM and this will allow Vivado Synthesis to pack the ROM into the block RAM.

AR# 57981
Date Created 10/16/2013
Last Updated 10/22/2013
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2013.3