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AR# 57982

Vivado Synthesis - fails with no error due to System Verilog parameter values

Description

A System Verilog test design can fail synthesis with no error message when certain parameter values are used such as 'x, '1, or '0.

module top (
output logic [31:0] dout [0:0]
);

 
sub #(
.PARAM('{'1}) // Fails
) u (
.dout(dout)
);
endmodule
 
module sub # (
parameter logic[32-1:0] PARAM [0:0] = '{'1}
  )
    (
output logic [31:0] dout [0:0]
); 
    assign dout = PARAM;
endmodule

 

 

 

Solution

In this scenario, the user is trying to replicate a parameter value to the entire bus width. 

The following alternative coding style can be used in Vivado 2013.2 & 2013.3 to work around this issue.

As shown below, the System Verilog parameter needs to be explicitly specified as the correct width (32). 

Also, PARAM(1'bx), PARAM(1'bz), or PARAM(1'b1) can be used to replace .PARAM('{'x}), .PARAM('{'z}), or .PARAM('{'1}) respectively.


module top (
output logic [31:0] dout [0:0]
);

sub #(
.PARAM({32{1}}) // WORKS!
) u (
.dout(dout)
);
endmodule
 

 

module sub # (
parameter logic[32-1:0] PARAM [0:0] = '{'1}
  )
    (
output logic [31:0] dout [0:0]
);
    assign dout = PARAM;
endmodule

 

This is fixed in Vivado 2013.4.

AR# 57982
Date Created 10/16/2013
Last Updated 09/05/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.2