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AR# 58020

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v14.0 - MMCM_LOCKED output needs to be connected to reset logic

Description

In Ethernet 1000BASE-X PCS/PMA or SGMII core v14.0, the MMCM_LOCKED output from the MMCM is not used to hold logic in reset until after the MMCM has finished locking.  

This was not an issue in the v13.0 core.

Solution

In the file <core_name>_resets.v/vhd add an input called "mmcm_locked". 

The <core_name>_resets module is instantiated in the <core_name>_support.v/vhd file.  

The added MMCM_LOCKED input should be driven by the mmcm_locked signal in <core_name>_support.v/vhd.

If using Verilog in the <core_name>_reset.v change:

  always@(posedge independent_clock_bufg or posedge reset)
      if (reset == 1'b1)
         pma_reset_pipe <= 4'b1111;
to:
  always@(posedge independent_clock_bufg or posedge reset or mmcm_reset)
      if (reset == 1'b1 || mmcm_locked==1'b0)
         pma_reset_pipe <= 4'b1111;


If using VHDL in the <core_name>_reset.vhd change:
  
process(mmcm_locked, reset, independent_clock_bufg)
   begin
     if (reset = '1' ) then
       pma_reset_pipe <= "1111";
to:
   process(mmcm_locked, reset, independent_clock_bufg)
   begin
     if (reset = '1' or mmcm_locked= '0' ) then
       pma_reset_pipe <= "1111";


Note: This was updated in the Vivado 2013.4 release of the core.

Linked Answer Records

Master Answer Records

AR# 58020
Date Created 10/17/2013
Last Updated 05/02/2014
Status Active
Type General Article
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII