UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58030

LogiCORE IP Aurora 8B10B v9.0 or earlier - Update Required for CLK_COR_MIN_LAT/CLK_COR_MAX_LAT Attributes

Description

Aurora 8B10B core when targeted to 7 series transceivers is found to have incorrect values for CLK_COR_MIN_LAT/CLK_COR_MAX_LAT attributes.

If you find any of the following symptoms with the core, please update the attribute values provided in this answer record .

  • Rx Buffer overflow/underflow
  • Channel bonding failure

Solution

Number Of Lanes Lane Width CLK_COR_MIN_LAT CLK_COR_MAX_LAT
16 2 26 29
16 4 52 59
15 2 26 29
15 4 52 59
14 2 26 29
14 4 52 59
13 2 24 27
13 4 48 55
12 2 24 27
12 4 48 55
11 2 22 25
11 4 44 51
10 2 22 25
10 4 44 51
9 2 20 23
9 4 40 47
8 2 20 23
8 4 40 47
7 2 18 21
7 4 36 43
6 2 18 21
6 4 36 43
5 2 18 21
5 4 32 39
4 2 18 21
4 4 32 39
3 2 18 21
3 4 28 35
2 2 18 21
2 4 28 35
1 2 12 15
1 4 24 31


Revision History

10/23/2013 - Initial release

AR# 58030
Date Created 10/18/2013
Last Updated 11/27/2013
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • Aurora 8B/10B