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AR# 58049

2013.2 Vivado GUI - Vivado does not take Verilog structural netlists with a .vm extension (from Synplify) as Verilog netlists


Synplify can generate structural Verilog netlists but gives them a .vm extension.

Vivado 2013.2 does not recognize these files as Verilog netlists.

How can I make Vivado recognize these files?


This is a known issue in 2013.2 and older versions.

In order to get these netlists to work in 2013.2 and older versions, you will need to either rename the file to a .v or set the file type of the .vm to "Verilog".

In 2013.3, Vivado recognizes the .vm file as Verilog and the Synthesized design can be opened successfully.

However, Vivado does not recognizes it as a 3rd party netlist.

It does not show up in the GUI as a default for the netlist source when adding sources to a project.

It is still under discussion how to handle the .vm file extension in Vivado.

In 2013.3, you can follow these steps to create a Post-synthesis project using the .vm file and open the Synthesized design.
  1. Create a new Post-synthesis project.
  2. On the "Add Sources" page, click "Add Files..." and select the .vm file. (You will need to select "All Files" for the "Files of type" in order to select the .vm)
  3. Go through the rest of the pages and manually select the target device.
  4. After the project is created, open the Synthesized design.
    You will be prompted to specify the top level name.
    Enter the top module name in the .vm file (not the .vm file name) and then the Synthesized design can be opened.
AR# 58049
Date 12/10/2014
Status Archive
Type General Article
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2012.4
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