Version Found: v2.2
Version Resolved and other Known Issues: See (Xilinx Answer 54643)
Are there any limitations in combinations of Target Language and Simulator Language?
In the current release, only MIXED option is supported for Simulator Language.
For Target Language, it could be either Verilog or VHDL. This limitation applies to all four supported simulators: Vivado, VCS, IUS and Questa.
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
10/23/2013 - Initial release