We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58052

7 Series Integrated Block Wrapper for PCI Express v2.2 - Supported combinations of Target Language and Simulator Language


Version Found: v2.2
Version Resolved and other Known Issues: See (Xilinx Answer 54643)

Are there any limitations in combinations of Target Language and Simulator Language?


In the current release, only MIXED option is supported for Simulator Language.

For Target Language, it could be either Verilog or VHDL. This limitation applies to all four supported simulators: Vivado, VCS, IUS and Questa.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
10/23/2013 - Initial release

AR# 58052
Date Created 10/21/2013
Last Updated 10/24/2013
Status Active
Type Known Issues
  • 7 Series Integrated Block for PCI Express (PCIe)