MIG 7 Series v2.0 Rev1 IP now supports IES and VCS simulations for Verilog designs only and simulations must be run stand-alone outside of the Vivado tool.
The scripts attached at the end of this answer record are targeted for the MIG 7 Series IP example design generated by running "Open IP Example Design" in the Vivado GUI. Any simulations of the User Design or custom designs will require the user to create their own scripts for simulations.
Steps for running the simulations scripts can be located in the readme.txt file inside the AR58057.zip attachment.
Note: QDRII+ memory models are required for simulations and must be obtained directly from the memory vendor.
For LPDDR2 simulations, the following error message will occur using VCS:
Error-[SE] Syntax error
Following verilog source has syntax error :
"../../user_design/rtl/controller/mig_7series_v2_0_arb_select.v", 402 token is '*)'
To remove this error message, the above line 'always @(/*AS*/*)' should be replaced with 'always @(*)' in the file mig_7series_v2_0_arb_select.v.
10/25/2013 - Initial release
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