We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58071

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.2 - Fatal error not flagged during completion buffer overflow


Version Found: v2.2
Version Resolved and other Known Issues: (Xilinx Answer 54645)

The Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.2 core, when configured to use the COMPLETION_SPACE = "8KB" option, does not correctly flag a fatal error for completion buffer overflow.


This is a known issue that will be fixed in a future release of the core.

In a typical operation, user logic should not issue read requests such that it gets a completion buffer overflow.

(Appendix B of PG023 has a section on Managing Receive Buffer Space for received completions). 

The error will manifest itself into another error; for example, a code 0110 (Invalid Tag, The completion does not match the tags of any outstanding request) in the Requester Completer descriptor.

To work around this issue, it is recommended to use 16KB completion space.

You should still make sure that the pending read requests do not result in completion buffer overflow, and should watch out for error indications like code 0110 in Requester Completer Descriptor.

Although a fatal error for completion buffer overflow is not flagged when configured to use COMPLETION_SPACE = "8KB" option (whereas it does when configured to use "16KB" instead), it is still specification-compliant as buffer overflow checking is an optional check as per the specification. 

This could make debug more difficult for some users.

The current default setting is 8KB. In the next release of the core, the default setting will be set to 16KB. Users needing a fatal error must switch to 16KB which will consume 4 extra block RAM compared to 8KB.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
10/23/2013 - Initial release

Linked Answer Records

Master Answer Records

AR# 58071
Date Created 10/21/2013
Last Updated 05/27/2014
Status Active
Type Known Issues
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)