UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58081

MIG 7 Series - How do you capture calibration results using triggers in the Vivado Lab Tools?

Description

The following error is generated when the trigger is armed during a reset if capturing the results of each stage of the MIG 7 series calibration using different calibration status triggers (i.e., dbg_wrlvl_start):

ERROR: [Labtools 27-1395] Unable to arm ILA "hw_ila_1". The core clock is slow or no core clock connected for this ILA or the ILA core may not meet timing.

This error only occurs in the Vivado Lab Tools; when using ChipScope with the ISE design tools, there are no errors.

How do you work around this error and capture the results as detailed in the Debugging DDR3/DDR2 Designs section of UG586?

Solution

This error occurs when the trigger is set to a '1'. The trigger mechanism in the Vivado Lab Tools is different from the ISE ChipScope tool. The moment a reset is given and the clock connected to ILA goes away, the ILA 2.0 will not accept any asynchronous trigger condition and this causes the error.

To work around this issue, set the trigger to look for a rising edge ('R') or falling edge ('F') with the radix set to "Binary". Using this trigger setting, the trigger can be armed, the reset applied and released, and the trigger will capture the desired ILA results.

Revision History
10/22/2013 - Initial release

AR# 58081
Date Created 10/22/2013
Last Updated 11/15/2013
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series