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AR# 58088

7 Series FPGAs Transceiver Wizard v3.0 - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the 7 series FPGAs Transceiver Wizard v3.0, released with the Vivado 2013.3 design tool.

Solution

  • Version 3.0
  • GTH Attributes and QPLL range - Refer to (Xilinx Answer 56332) and DS183
  • Updated GTZ Attributes and Clocking
  • Updated timing constraints (XDC) to resolve Critical Warnings and added support for out-of-context synthesis
  • Updated timing constraints for recovered clocks in IP level.For details, refer to Migrating and Upgrading section of Product Guide - pg168-gtwizard.pdf
  • Updated TX and RX FSM to fix MMCM lock synchronization and simulation issues (for all GTs)
  • GTX TX buffer bypass is enabled in both Manual & Auto modes for single lane as per UG476.
  • Added check in the GUI to disallow mixed encode/decode for TX and RX
  • Added GUI option to include or exclude Vivado Lab tools support for debug
  • Removed LPM and DFE Manual mode option from the GUI
  • Added checks to limit DRP frequency selection
  • Protocol templates updated for -- Display port, sRIO gen2, CEI6, Aurora 8B10b
  • Reduced warnings in synthesis and simulation
  • Enhanced Support for IP Integrator
  • Added support for Cadence IES and Synopsys VCS simulators
  • Updated clock synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from met stability
  • Added GUI option to include or exclude shareable logic resources. For details, refer to Upgrading in Vivado Design Suite section of Product Guide - pg168-gtwizard.pdf
  • Added optional ports to enable transceiver core debug - Refer to pg168-gtwizard.pdf
  • Updated line rate ranges for A7 Wire bond package from 5.4G to 6.25G
  • Added support for XC7Z015 and XC7A75T
  • Moved clock constraints for the recovered clocks to core level xdc file from example design level
  • Added optional vivado (ILA and VIO) lab tools support for core debug in example design
AR# 58088
Date Created 10/22/2013
Last Updated 10/30/2013
Status Active
Type Release Notes
Devices
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • More
  • Virtex-7
  • Virtex-7 HT
  • Less
Tools
  • Vivado Design Suite - 2013.3
IP
  • 7 Series FPGAs Transceivers Wizard