We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 58089

LogiCORE IP JESD204B v5.0 - RX Register Address decide unintended offset for multi-lane cores greater than 2 lanes


The RX core has an issue with the multi-lane cores greater than 2 having their base address set incorrectly when using the JESD204 v5.0 core in Vivado 2013.3 tool.


With reference to Table 2-8 in PG066 (Address Map), the Lane specific read-only register blocks should be at :

0x800>0x840 (lane 1)  - base address is correct as documented
0x880 (lane 2)  - actual base address is 0x87C
0x8C0 (lane 3) - actual base address is 0x8B8
0x900 (lane 4) - actual base address is 0x8F4
0x940 (lane 5) - actual base address is 0x930
0x980 (lane 6) - actual base address is 0x96C
0x9c0 (lane 7) - actual base address is 0x9AB

This issue will be fixed in Vivado Design Suite 2013.4.

Revision History
10/30/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54480 LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 58089
Date Created 10/22/2013
Last Updated 10/30/2013
Status Active
Type General Article
  • JESD204